Embodiments relate to a semiconductor device and a method of fabricating a semiconductor device, which may improve a yield rate.
To fabricate a semiconductor device, an inter-metal dielectric layer, for example including FSG (fluorine silicate glass), may be formed through a BEOL (Back-End-Of-Line) process. A metal interconnection, for example including copper (Cu), may then be formed on the inter-metal dielectric layer. In such a semiconductor device, a damascene process may be used, instead of a metallization process using a subtractive scheme, to form a metal interconnection that may include aluminum (Al). Thus, although the BEOL process has been changed, the process has not yet been optimized.
Since the process conditions have not yet been optimized, a yield rate of a semiconductor device may be significantly lowered.